Static random access memories are widely known in the semiconductor technology. A schematic of a generic SRAM cell is shown in FIG. 1. The cell is made of a cross coupled inverter, each inverter having a pulldown transistor T1 or T2 and a load p1 or p2, and a pair of transfer transistors T3,T4. The gate electrode of T1 is connected to the drain of T2 and the gate electrode of T2 is connected to the drain of T1 to provide the flip-flop operation. The load device p1,p2 may be a depletion or enhancement transistor or a high value resistor as the case for the present invention. The load devices p1 and p2 are connected to the power supply V.sub.dd on one side and to the drain of drive transistors T1, T2 respectively. The purpose of the resistor load p1,p2 and the power supply V.sub.dd is to counteract the effect of charge leakage at the drains of the drive and transfer transistors (nodes N1 and N2). The gates of the transfer transistors T3, T4 are connected to a WORD line 8 and are switched ON by asserting the WORD line 8. The drain/source contacts of the transfer transistors are connected between the nodes N1,N2 and BIT lines 5,6 respectively.
SRAM operation is well known. In brief, the charge (voltage) in nodes N1 and N2 represent the logic state of the cell. For example, to write a data of "1" in node N1, the bit line 5 is precharged to a desired voltage and the word line 8 is asserted. Node N1 is charged up and drives N2 to a "no charge" or a low state. To read the cell, bit lines 5 and 6 are precharged and word line 8 is asserted. The bit line 6 is discharged through transistor T4 and T2 and the transient is sensed by a sense amplifier external to the cell.
A four transistor (4T) SRAM uses a high value resistor as its load device. The attraction of 4T SRAM is the potential for reduced cell size compared to a 6T SRAM (load devices are transistors). The primary function of the load resistor is to supply enough current to compensate for the junction leakage and maintain the charge in the node. junction leakage current typically range from femtoampere to picoampere (10.sup.-15 to 10.sup.-12 A) for FETs fabricated under contamination free conditions, which is the minimum current required from the loaded (p1,p2) power supply V.sub.dd. The maximum resistor value acceptable is in the range of 10.sup.2 to 10.sup.15 ohms, assuming a V.sub.dd of 3 to 5 volts. The value of the resistor, in turn is affected by availability of material that has very high intrinsic resistance and the cell area available for resistor layout. In addition, the resistor material and process should be compatible with silicon manufacturing.
Intrinsic polysilicon, a suitable material for high value resistors, can be used in selected thickness range to provide sheet resistance as high as a few hundred giga ohms, but it takes up a large part of cell area. Since read operation causes temporary partial change in charge stored in the nodes N1 and N2, a higher current from the loaded power supply can restore the charge in the nodes quickly to its "write value". This restoration may determine how fast data can be repeatedly read. Also, soft-error susceptibility is increased when the charge in the node is off its maximum. Again, fast charging from the power supply can reduce soft error occurrence as the nodes will be charged to full voltage and is less susceptible than if the charge levels were lower. A soft error is caused when the electron-hole current generated in the silicon from ionizing radiation upsets the charge in the node and causes the cell to flip. These considerations suggest use of a lower value leakage resistor. These problems are known and are reviewed in an article titled, "Cell Technology Directions For Advanced MPUs and Other Memory Embedded Logic Devices", by Kinugawa and Katama in 1993 IEEE IEDM, pp 37-40. However, the primary attraction of a 4T-SRAM continues to be its small size and lower manufacturing cost for stand alone memory. It has been the goal of many researchers to develop resistors of higher value so that a high value resistor can be easily integrated into the SRAM process using minimum chip area. Hashimoto (U.S. Pat. No. 4,849,248) teaches ion implanting silicon into SiO.sub.2 and annealing to obtain segregates (islands) of silicon in an SiO.sub.2 film, thus forming high value resistors. Blanchard (U.S. Pat. No. 4,868,537) teaches implanting ions of Cesium into the SiO.sub.2 layer to form resistors. Tanaka et al., (U.S. Pat. No. 5,049,970) teaches ion injecting silicon ions and conductive impurities in the oxide film to form a resistor. Sandhu et al., (U.S. Pat. No. 5,235,312) teaches a method of oxidizing a thin layer of polysilicon so as to oxidize all individual grains to form a high resistance layer. Yamoto et al., (U.S. Pat. No. 4,702,937) describes two layers of polysilicon with an interspersed oxide layer, thus forming a high value resistor suitable for SRAM applications.
Harrington III (U.S. Pat. No. 4,950,620) teaches a process for making a compact four transistor SRAM using arsenic implantation in selected areas of the dielectric overlying the substrate. In Harrington's process, the dielectric mask for implantation and the contact opening are not self-aligned leading to a larger cell size. Yau et al. (U.S. Pat. No. 4,786,612) teaches a method of forming Si rich silicon nitride semi-insulating film by PECVD deposition, between two conducting layers. In one of the embodiments, Yau forms the semi-insulating layer over a tungsten silicide layer. Yau's method forms a vertical resistor, but suffers from the fact that the vertical resistor is located away from the diffusion contact regions, thereby increasing the SRAM cell size. Further, the PECVD deposited resistive layer is patterned using a separate mask than the contacting layer and the process is not self-aligned.
Manning (U.S. Pat. Nos. 5,159,430 and 5,232,865) teaches forming polysilicon filled vias in contact with Si device and subsequently implanting oxygen or nitrogen to increase the resistance of the polysilicon stud as shown in FIG. 2. A high temperature anneal at about 950 C is carried out to stabilize the resistor value. Since load resistors are required only in some of the contacts, Manning's process will involve fabricating the resistor contacts in a separate step. i.e it will take two mask steps to fabricate all the contacts. An annealing temperature of 950 C is high for very shallow doped devices, which can cause dopant spreading and affect Junction widths. It is therefore preferable to form a high resistor using a lower temperature process. These prior art methods teach forming a high value resistor by either introducing silicon in an SiO.sub.2 layer or introducing oxygen or nitrogen into a Si layer, i.e by forming off-stoichiometric structures. A detailed discussion of enhanced conduction of insulators can be found in an article entitled "High current injection into SiO2 from Si rich SiO.sub.2 films and experimental applications", by D. J. DiMaria and D. W. Dong, Journal of Applied Physics 51(5) May 1980, pp 2722-2735.
Another prior art method by Mitsuhashi et al., (U.S. Pat. No. 5,093,706) involves fabricating discrete resistor layer, comprising a stacked thermal oxide and nitride layers, over the diffusion region, coating with an insulating layer and forming a contact opening in the insulating layer to the resistor as shown in FIG. 3. Referring to FIG. 3, a highly resistive leaky layer 15a, 15b is formed directly over the diffusion region of an FET transistor and cladded with polysilicon 18. An insulator layer 20 is deposited on the substrate, and an opening 22 is etched in insulator 20 to make contact to the polysilicon overlying the resistor. The resistive, layers 15a, 15b functions as a vertical resistor, but the contact area from opening 22 has to be designed smaller in order to fully land the contact electrode 24. Further, masking processes used for etching contact opening 22 and for etching resistor stack 15a, 15b, are printed to minimum lithographic ground rules (critical masks), which increases the process complexity. Critical masks are difficult to align and process than non-critical masks. Mitsuhashi's process has a further disadvantage of requiring two separate masks with overlay tolerance which increases the cell size.
SRAMs are susceptible to soft errors. A soft error occurs, when an ionizing radiation strikes the Si substrate and creates free electrons and holes. The free electrons and holes migrate under electric fields to different parts of devices, and can change the state of a memory cell or interfere with reading data from cells. Load resistor SRAMs may be more susceptible than 6T-SRAMs if the current supply to restore soft error ionization is too small, i.e on the order of picoampere per cell. However, use of high load current can lead to excessive power consumption. There is therefore a need to have an improved high resistance SRAM that requires a steady low current, is compatible with low power supplies, takes up very little space, has improved soft error tolerance and has low process complexity.